AMD and 8 core fiasco

Bear in mind, this isn’t as deceptive at it sounds and will probably be thrown out.
Bulldozer modules have two integer cores that can handle independent threads and a singe FPU core, so there are actually 12 “cores” in a 4-module chip like an FX-8350, and each Intel core actually has two “cores”. This concept of cores began with Intel’s 286 architecture and its separate FPU. Intel does a 1:1 mapping of integer to FPU, but AMD, since FPU operations are fewer and farther between than Integer ones, decided to reduce transistor counts by going 2:1.

To compare in simple terms a bulldozer module with an Intel CPU core:
Thread 1 enters each core. It begins the instruction pipeline
Thread 2 enters each core:
If it is an integer operation (most ops are), on the AMD chip it starts the pipeline on core 2. If it is a floating point operation, it waits until the operation completes the pipeline and then is processed.

On the Intel chip, the op is staged to core 1; if the op is already in the core’s cache, it uses cached information and emulates a second thread (this is Hyperthreading).

If it is not in cache, it remains in a staged state until the current op completes the instruction pipeline. The previous operation is added to the cache (until it is full) and is available for future threads.

This is why Hyperthreading is more effective in some use cases, and not in others.

Hopefully that clears up some things on this subject. AMD chips can indeed run 8 threads under most circumstances, and is a very effective server solution (especially in high thread applications like virtualization); it also explains why Xeon 16-core chips cost 6-8 times as much as Opteron ones do.


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